AT24C02A_14 Datasheet, PDF (8/16 Pages) ATMEL Corporation – Write Protect Pin for Hardware Data Protection

of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as
a microcontroller, must terminate the write sequence with a stop condition. At this time,
the EEPROM enters an internally-timed write cycle, t_WR, to the nonvolatile memory. All
inputs are disabled during this write cycle, and the EEPROM will not respond until the
write is complete, as shown in Figure 8.
Figure 8. Byte Write
S
W
T
R
A
I
R
T
DEVICE
ADDRESS
T
E
WORD ADDRESS
DATA
S
T
O
P
SDA LINE
M
LRA M
LA
A
S
S/C S
SC
C
B
BW K B
BK
K
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K
EEPROM device is capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(2K) or fifteen (4K) more data words. The EEPROM will respond with a “0” after each
data word received. The microcontroller must terminate the page write sequence with a
stop condition, as shown in Figure 9.
Figure 9. Page Write
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E _{WORD ADDRESS (n)}
DATA (n)
DATA (n + 1)
S
T
O
DATA (n + x)
P
SDA LINE
M
LR A
A
A
A
A
S
S/ C
C
C
C
C
B
BW K
K
K
K
K
The data word address lower three (2K) or four (4K) bits are internally incremented fol-
lowing the receipt of each data word. The higher data word address bits are not
incremented, retaining the memory page row location. When the word address, inter-
nally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (2K) or sixteen (4K) data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will
be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0” allowing the read or write sequence to continue.
8 AT24C02A/04A
5083D–SEEPR–4/07