AT24C02A_14 Datasheet, PDF (7/16 Pages) ATMEL Corporation – Write Protect Pin for Hardware Data Protection

Figure 6. Output Acknowledge
AT24C02A/04A
Device Addressing
The 2K and 4K EEPROM devices all require an 8-bit device address word following a
start condition to enable the chip for a read or write operation, as shown in Figure 7.
Figure 7. Device Address
2K
1 0 1 0 A₂ A₁ A₀ R/W
MSB
LSB
4K
1 0 1 0 A₂ A₁ P0 R/W
Write Operations
5083D–SEEPR–4/07
The device address word consists of a mandatory “1”, “0” sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.
The next three bits are the A2, A1, and A0 device address bits for the 2K EEPROM.
These three bits must compare to their corresponding hardwired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a
memory page address bit. The two device address bits must compare to their corre-
sponding hardwired input pins. The A0 pin is no-connect.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the chip will return to a standby state.
BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgement. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
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