AT24C02A_14 Datasheet, PDF (6/16 Pages) ATMEL Corporation – Write Protect Pin for Hardware Data Protection

Figure 4. Bus Timing
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
Figure 5. Write Cycle Timing
SCL
SDA
8th BIT
ACK
Note:
WORDn
STOP
CONDITION
(1)
t_wr
START
CONDITION
The write cycle time t_WR is the time from a valid stop condition of a write sequence to the end of the interval clear/write cycle.
6 AT24C02A/04A
5083D–SEEPR–4/07