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AT17N040_14 Datasheet, PDF (8/18 Pages) ATMEL Corporation – Simple Interface to SRAM FPGAs
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DC Characteristics
VCC = 3.3V ± 10%
Symbol
VIH
VIL
VOH
VOL
VOH
VOL
ICCA
IL
Description
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage
(IOH = -2.5 mA)
Low-level Output Voltage
(IOL = +3 mA)
High-level Output Voltage
(IOH = -2 mA)
Low-level Output Voltage
(IOL = +3 mA)
Supply Current, Active Mode
Input or Output Leakage Current
(VIN = VCC or GND)
ICCS
Supply Current, Standby Mode
AT17N256
Min Max
2.0
VCC
0
0.8
AT17N512/
AT17N010
Min Max
2.0
VCC
0
0.8
AT17N002/
AT17N040
Min Max
2.0
VCC
0
0.8
Units
V
V
2.4
2.4
2.4
V
Commercial
0.4
0.4
0.4
V
2.4
2.4
2.4
V
Industrial
0.4
0.4
0.4
V
5
5
5
mA
-10
10
-10
10
-10
10
µA
Commercial
50
100
150
µA
Industrial
100
100
150
µA
AC Characteristics
VCC = 3.3V ± 10%
AT17N256
AT17N512/010/002/040
Commercial Industrial Commercial Industrial
Symbol Description
Min Max Min Max Min Max Min Max
TOE(1)
TCE(1)
TCAC(1)
TOH
TDF(2)
TLC
THC
TSCE
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK
(to guarantee proper counting)
50
55
50
55
60
60
55
60
75
80
55
60
0
0
0
0
55
55
50
50
25
25
25
25
25
25
25
25
35
60
30
35
THCE
CE Hold Time from CLK
(to guarantee proper counting)
0
0
0
0
THOE
FMAX
Notes:
OE High Time (guarantees counter is reset) 25
25
25
25
Maximum Clock Frequency
10
10
15
10
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
8 AT17N256/512/010/002/040
3020C–CNFG–08/07
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