AT17N040_14 Datasheet, PDF (5/18 Pages) ATMEL Corporation – Simple Interface to SRAM FPGAs

AT17N256/512/010/002/040
Pin Description
Name
I/O
DATA
I/O
CLK
I
RESET/OE
I
CE
I
GND
DC
O
DC
O
VCC(SER_EN) I
V_CC
DATA
CLK
RESET/OE
CE
GND
VCC(SER_EN)
V_CC
NC
DC
AT17N256
8
DIP/
SOIC
20
SOIC
1
1
2
3
3
8
4
10
5
11
6
13
–
–
7
18
8
20
AT17N512/
AT17N010
8
20
DIP
SOIC
1
1
2
3
3
8
4
10
5
11
6
13
–
–
7
18
8
20
AT17N002
20
SOIC
1
3
8
10
11
13
–
18
20
44
TQFP
40
43
13
15
18
21
23
35
38
AT17N040
44
TQFP
40
43
13
15
18
21
23
35
38
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
Ground pin. A 0.2 µF decoupling capacitor between V_CC and GND is recommended.
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V_CC.
3.3V (±10%) Commercial and Industrial power supply pin.
NC pins are No Connect pins, which are not internally bonded out to the die.
DC pins are No Connect pins internally connected to the die. It is not recommended to
connect these pins to any external signal.
5
3020C–CNFG–08/07