AT17N040_14 Datasheet, PDF (6/18 Pages) ATMEL Corporation – Simple Interface to SRAM FPGAs

FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17N
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the master serial mode configuration of Atmel AT17N series
configuration memories, pin compatible with Spartan-II, Spartan-IIE and Spartan XL
OTP PROMs.
Control of
Configuration
Most connections between the FPGA device and the AT17N Serial EEPROM are simple
and self-explanatory.
• The DATA output of the AT17N series configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17N series
configurator.
• SER_EN must be connected to V_CC (except during ISP).
• The CE and OE/Reset are driven by the FPGA to enable output data buffer of the
EEPROM.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at V_CC supply
only. Programming super voltages are generated inside the chip.
Standby Mode
The AT17N series configurators enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17N256 configurator consumes less than 50 µA of
current at 3.3V (100 µA for the AT17N512/010 and 200 µA for the AT17N002/040).
6 AT17N256/512/010/002/040
3020C–CNFG–08/07