AT17C512 Datasheet, PDF (8/9 Pages) ATMEL Corporation – FPGA Configuration E2PROM Memory

AC Characteristics for AT17LV512/010
V_CC = 3.3V ± 10%
Commercial/Industrial
Military
Symbol
T_OE(2)
T_CE(2)
T_CAC(2)
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Min
Max
Min
Max
50
55
55
60
55
60
T_OH
T_DF(3)
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
0
0
50
50
T_LC
CLK Low Time
25
25
T_HC
CLK High Time
25
25
T_SCE
CE Setup Time to CLK (to guarantee proper counting)
30
35
T_HCE
CE Hold Time to CLK (to guarantee proper counting)
0
0
T_HOE
OE High Time (Guarantees Counter Is Reset)
25
25
F_MAX(4) MAX Input Clock Frequency
15
10
V_RDY
Ready Pin Open Collector Voltage
1.2
2.2
1.2
2.2
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
4. During cascade F_MAX = 12.5 MHz.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
V
AC Characteristics for AT17LV512/010 When Cascading
V_CC = 3.3V ± 10%
Commercial/Industrial
Symbol
T_CDF(3)
T_OCK(2)
T_OCE(2)
T_OOE(2)
Description
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Min
Max
50
50
35
35
Military
Min
Max
50
55
40
35
Units
ns
ns
ns
ns
8 AT17C/LV512/010