AT17C512 Datasheet, PDF (1/9 Pages) ATMEL Corporation – FPGA Configuration E2PROM Memory

Features
• E² Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store
Configuration Programs For Field Programmable Gate Arrays (FPGA)
• Simple Interface to SRAM FPGAs
• Compatible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K,
EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola
MPA1000 FPGAs
• Cascadable To Support Additional Configurations or Future Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available In PLCC Package (Pin Compatable across Product Family)
• In-System Programmable Via 2-Wire Bus
• Emulation of 24CXX Serial EPROMs
• Available in 3.3V ± 10% LV and 5V Versions
• System Friendly READY Pin
Description
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configu-
ration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The high-density AT17 Series is pack-
aged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The high-density
AT17 Series organization supplies enough memory to configure one or multiple
smaller FPGAs. The user can select the polarity of the reset function by programming
one EEPROM byte. The devices also support a write protection mode and a system
friendly READY pin, which signifies a “good” power level to the device and can be
used to ensure reliable system power-up.
The high-density AT17 Series can be programmed with industry-standard program-
mers, and the Atmel ATDH2200 Programming board.
FPGA
Configuration
E²PROM
Memory
512K and 1M
AT17C512
AT17LV512
AT17C010
AT17LV010
Pin Configurations
20-Pin PLCC
D
A
V
N T NCN
CACCC
3 2 1 20 19
CLK 4
18 NC
WP1 5
17 SER_EN
RESET/OE 6
16 NC
WP2 7
1 5 READY
CE 8
14 CEO
9 10 11 12 13
NGNNN
CNCCC
D
Rev. 0944A-A–12/97
1