AT17C512 Datasheet, PDF (7/9 Pages) ATMEL Corporation – FPGA Configuration E2PROM Memory

AT17C/LV512/010
.
AC Characteristics for AT17C512/010
V_CC = 5V ± 5% Commercial / V_CC = 5V ± 10% Ind./Mil
Symbol
T_OE(2)
T_CE(2)
T_CAC(2)
T_OH(2)
T_DF(3)
T_LC
T_HC
T_SCE
T_HCE
T_HOE
F_MAX
V_RDY
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLK (to guarantee proper counting)
OE High Time (Guarantees Counter Is Reset)
MAX Input Clock Frequency
Ready Pin Open Collector Voltage
Commercial/Industrial
Min
Max
30
45
50
0
50
20
20
20
0
20
15
1.2
2.2
Military
Min
Max
35
45
50
0
50
20
20
25
0
20
15
1.2
2.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
V
AC Characteristics for AT17C512/010 When Cascading
V_CC = 5V± 5% Commercial / V_CC = 5V ± 10% Ind./Mil.
Commercial/Industrial
Military
Symbol
Description
Min
Max
Min
Max
T_CDF ⁽³⁾
CLK to Data Float Delay
50
50
T_OCK(2)
CLK to CEO Delay
35
40
T_OCE(2)
CE to CEO Delay
35
35
T_OOE(2)
RESET/OE to CEO Delay
30
30
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
Units
ns
ns
ns
ns
7