SAM-G53N_14 Datasheet, PDF (796/949 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

33.7.9 USART Interrupt Mask Register
Name:
US_IMR
Address: 0x40024010
Access: Read-only
31
30
29
28
27
26
25
–
–
–
–
–
–
–
23
22
21
20
19
18
17
–
–
–
–
CTSIC
–
–
15
14
13
12
11
10
9
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
For SPI specific configuration, see Section 33.7.10 ”USART Interrupt Mask Register (SPI_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• RXBRK: Receiver Break Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
• ENDTX: End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
• RXBUFF: Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
• CTSIC: Clear to Send Input Change Interrupt Mask
24
–
16
–
8
TIMEOUT
0
RXRDY
796
SAM G53G / SAM G53N [DATASHEET]
Atmel-11240E-ATARM-SAM-G53G-SAM-G53N-Datasheet_17-Oct-14