SAM-G53N_14 Datasheet, PDF (42/949 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

11.4.1.16Control Register
Name:
CONTROL
Access: Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
–
23
22
21
20
19
18
17
16
–
15
14
13
12
11
10
9
8
–
7
6
5
4
3
2
1
0
–
FPCA
SPSEL
nPRIV
The Control Register controls the stack used and the privilege level for software execution when the processor is in Thread
mode and indicates whether the FPU state is active.
• FPCA: Floating-point Context Active
Indicates whether the floating-point context is currently active:
0: No floating-point context active.
1: Floating-point context active.
The Cortex-M4 uses this bit to determine whether to preserve the floating-point state when processing an exception.
• SPSEL: Active Stack Pointer
Defines the current stack:
0: MSP is the current stack pointer.
1: PSP is the current stack pointer.
In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4 updates this bit automatically on exception
return.
• nPRIV: Thread Mode Privilege Level
Defines the Thread mode privilege level:
0: Privileged.
1: Unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the Control
Register when in Handler mode. The exception entry and return mechanisms update the Control Register based on the
EXC_RETURN value.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack, and the kernel and
exception handlers use the main stack.
By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:
• Use the MSR instruction to set the Active stack pointer bit to 1, see “MSR”, or
• Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 11-10.
42 SAM G53G / SAM G53N [DATASHEET]
Atmel-11240E-ATARM-SAM-G53G-SAM-G53N-Datasheet_17-Oct-14