ATAR092 Datasheet, PDF (77/107 Pages) ATMEL Corporation – Low-current Microcontroller for Wireless Communication

ATAR092/ATAR892
Combination Mode 8: Manchester Demodulation/ Pulse-width Demodulation
SSI mode 1:
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3
For Manchester demodulation, the edge detection stage must be programmed to detect each
edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used
to generate the shift clock for the SSI. A compare register 1 match event defines the correct
moment for shifting the state from the input T3I as the decoded bit into shift register. After that,
the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can be used to detect a time error and handle it with an interrupt routine.
Before activating the demodulator mode the timer and the demodulator stage must be synchro-
nized with the bitstream. The Manchester code timing consists of parts with the half bitlength
and the complete bitlength. A synchronization routine must start the demodulator after an inter-
val with the complete bitlength.
The counter can be driven by any internal clock source. The output T3O can be used by Timer 2
in this mode. The Manchester decoder can also be used for pulse-width demodulation. The input
must programmed to detect the positive edge. The demodulator and timer must be synchronized
with the leading edge of the pulse. After that a counter match with the compare register 1 shifts
the state at the input T3I into the shift register. The next positive edge at the input restarts the
timer.
Figure 5-56. Manchester Demodulation
Timer 3
Mode
Synchronize
Manchester Demodulation Mode
T3I
1
0
1
1
1
0
0
1
1
0
T3EX
SI
CM3 = SCI
SR-DATA
1
BIT 0
1
BIT 1
1
BIT 2
0
BIT 3
0
BIT 4
1
BIT 5
10
BIT 6
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4535E–4BMCU–05/07