ARM920T_14 Datasheet, PDF (74/350 Pages) ATMEL Corporation – Technical Reference Manual

Memory Management Unit
3.5 Fault address and fault status registers
On a Data Abort, the MMU places an encoded 4-bit value, FS[3:0], along with the 4-bit
encoded domain number, in the data FSR. Similarly, on a Prefetch Abort, in the prefetch
FSR, intended for debug purposes only. In addition, the MVA associated with the Data
Abort is latched into the FAR. If an access violation simultaneously generates more than
one source of abort, they are encoded in the priority given in Table 3-9. The FAR is not
updated by faults caused by instruction prefetches.
3.5.1
Fault status
Table 3-9 describes the various access permissions and controls supported by the data
MMU and details how these are interpreted to generate faults.
Table 3-9 Priority encoding of fault status
Priority Source
Size Status Domain FAR
Highest Alignment
-
b00x1 Invalid
Lowest
Translation
Domain
Permission
External abort on noncachable nonbufferable
access or noncachable bufferable read
Section b0101
Page b0111
Section b1001
Page b1011
Section b1101
Page b1111
Section b1000
Page b1010
Invalid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
MVA of access causing
abort
MVA of access causing
abort
MVA of access causing
abort
MVA of access causing
abort
MVA of access causing
abort
Note
For data FSR only, alignment faults can write either b0001 or b0011 into FS[3:0].
Invalid values in domains 3:0 can occur because the fault is raised before a valid domain
field has been read from a page table descriptor. Any abort masked by the priority
encoding can be regenerated by fixing the primary abort and restarting the instruction.
For instruction FSR only, the same priority applies as for the data FSR, except that
alignment faults cannot occur, and external aborts apply only to noncachable reads.
3-22
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