ARM920T_14 Datasheet, PDF (40/350 Pages) ATMEL Corporation – Technical Reference Manual

Programmer’s Model
Register 1 bits [31:30] select the clocking mode of the ARM920T, as shown in
Table 2-11.
Table 2-11 Clocking modes
Clocking mode iA nF
FastBus mode
Synchronous
Reserved
Asynchronous
00
01
10
11
Enabling the MMU
You must take care with the address mapping of the code sequence used to enable the
MMU (see Enabling the MMU on page 3-29).
See Enabling and disabling the ICache on page 4-6 and Enabling and disabling the
DCache and write buffer on page 4-10 for the restrictions and the effects of having
caches enabled with the MMU disabled.
2.3.6
Register 2, translation table base (TTB) register
This is the Translation Table Base (TTB) register, for the currently active first-level
translation table. The contents of register 2 are shown in Table 2-12.
Table 2-12 Register 2, translation table base
Register
bits
Function
31:14
13:0
Pointer to first-level translation
table base. Read/write.
Reserved:
Read = Unpredictable.
Write = Should be zero.
Reading from register 2 returns the pointer to the currently active first-level translation
table in bits [31:14]. Writing to register 2 updates the pointer to the first-level translation
table from bits [31:14] of the written value.
Bits [13:0] should be zero when written, and are unpredictable when read.
2-14
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ARM DDI 0151C