ARM920T_14 Datasheet, PDF (147/350 Pages) ATMEL Corporation – Technical Reference Manual

Coprocessor Interface
7.3 MCR/MRC
MCR/MRC cycles look very similar to STC/LDC. An example with a busy-wait state is shown
in Figure 7-3.
ARM processor pipeline
Coprocessor pipeline
CPCLK
Decode
Execute
(WAIT)
Execute
(LAST)
Memory
Write
Decode
Execute
(WAIT)
Execute
(LAST)
Memory
Write
CPID[31:0]
MCR/
MRC
nCPMREQ
CPPASS
CPLATECANCEL
CHSDE[1:0]
WAIT
CHSEX[1:0]
LAST Ignored
CPDOUT[31:0]
LDC/MCR
CPDIN[31:0]
STC/MRC
Figure 7-3 ARM920T MCR/MRC transfer timing
ARM DDI 0151C
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