ATTINY40 Datasheet, PDF (73/216 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 4K Bytes In-System Programmable Flash

ATtiny40
11.7.4
The extreme values for the OCR0A Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A[1:0]
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0x to toggle its logical level on each Compare Match (COM0x[1:0] = 1). The waveform
generated will have a maximum frequency of ₀ = f_{clk_I/O}/2 when OCR0A is set to zero. This fea-
ture is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
Phase Correct PWM Mode
The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and OCR0A when WGM0[2:0] = 5. In non-
inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-
counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation
has lower maximum operation frequency than single slope operation. However, due to the sym-
metric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
Figure 11-7. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
8263A–AVR–08/10
TCNTn
OCn
OCn
Period
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
1
2
3
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 11-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating
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