ATTINY40 Datasheet, PDF (43/216 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 4K Bytes In-System Programmable Flash

ATtiny40
9.3 Register Description
9.3.1
MCUCR – MCU Control Register
The MCU Control Register contains bits for controlling external interrupt sensing and power
management.
Bit
7
6
5
4
3
2
1
0
0x3A
ISC01 ISC00
–
BODS
SM2
SM1
SM0
SE
MCUCR
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:6 – ISC0[1:0]: Interrupt Sense Control
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 9-2. The value on the INT0 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
ISC01
0
0
1
1
Interrupt 0 Sense Control
ISC00 Description
0
The low level of INT0 generates an interrupt request.
1
Any logical change on INT0 generates an interrupt request.
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
9.3.2
GIMSK – General Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
0x0C
–
PCIE2
PCIE1
PCIE0
–
–
–
INT0
GIMSK
Read/Write
R
R/W
R/W
R/W
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 6 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT[17:12] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT[17:12] pins are enabled individually by the PCMSK2 Register.
• Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT[11:8] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT[11:8] pins are enabled individually by the PCMSK1 Register.
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