SAM7S64_14 Datasheet, PDF (710/775 Pages) ATMEL Corporation – Internal High-speed Flash

40.20.2 Parallel Input/Output Controller (PIO)
40.20.2.1 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31
When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabi-
lizes at VPull-up.
Vpull-up
VPull-up Min
VDDIO - 0.65 V
VPull-up Max
VDDIO - 0.45 V
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V and 25 µA at
1.8V.
I Leakage
Parameter
I Leakage at 3,3V
I Leakage at 1.8V
Typ
2.5 µA
1 µA
Max
45 µA
25 µA
Problem Fix/Workaround
It is recommended to use an external pull-up if needed.
40.20.2.2 PIO: Drive Low NRST, PA0-PA16 and PA21-PA31
When NRST or PA0-PA16 and or PA21-PA31 are set as digital inputs with pull-up enabled, driving the I/O with an
output impedance higher than 500 ohms may not drive the I/O to a logical zero.
Problem Fix/Workaround
Output impedance must be lower than 500 ohms.
40.20.3 Pulse Width Modulation Controller (PWM)
40.20.3.1 PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is
directly modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Counter Register before writing the update register.
40.20.3.2 PWM: Update when PWM_CPRDx = 0
When Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround
Do not write 0 in the period register.
40.20.3.3 PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1.
Problem Fix/Workaround
None.
40.20.3.4 PWM: Constraints on Duty Cycle Value
Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode
may change the polarity of the signal.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
710