SAM7S64_14 Datasheet, PDF (338/775 Pages) ATMEL Corporation – Internal High-speed Flash

See Figure 30-24 on page 338.
30.9.4.2 Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as
soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when
reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR
is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
See Figure 30-25 on page 339.
30.9.4.3 Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See Figure 30-27 on page 341 and Figure 30-28 on page 342.
30.9.4.4 General Call
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the
new address programming sequence.
See Figure 30-26 on page 339.
30.9.5 Data Transfer
30.9.5.1 Read Operation
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave
address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR
register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 30-24 on page 338 describes the write operation.
Figure 30-24. Read Access Ordered by a MASTER
SADR does not match,
TWI answers with a NACK
SADR matches,
TWI answers with an ACK
ACK/NACK from the Master
TWD
TXRDY
NACK
SVACC
SVREAD
EOSVACC
S ADR R NA DATA NA P/S/Sr SADR R A DATA A
Write THR
A DATA NA S/Sr
Read RHR
SVREAD has to be taken into account only while SVACC is active
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
338