U5021M_05 Datasheet, PDF (7/11 Pages) ATMEL Corporation – Digital Window Watchdog Timer

Figure 5-1. State Diagram
Reset state
U5021M
time out t ₀
Mode switch
state
mode = 0
Short window
disable state
mode = 1
mode = 0
Long window
disable state
time out t ₁
time out t ₂
trg_ok = 1
mode = 1 ^{mode = 0}
time out t ₄
trg_ok = 1
time out t ₆
trg = 0
time out t ₃
Short window
enable state
Reset out
state
trg_err = 1
trg_err = 1
Long window
enable state
time out t ₅
or
wedge = 1
trg = 0
or wedge = 1
Notes:
• "mode" and "trg" are the debounced input signals from the pins MODE and TRG
• trg_ok = 1 after the rising edge of the trg signal
• trg_err = 1 when the trg signal low period is too long
• wedge = 1 after detecting the debounced changing of a signal level from the WUP pin
• Every state change restarts the internal timer
• If a state change is generated from an external debounced pin signal exactly one clock cycle before the internal
timer initiates a state change itself, the state machine changes its state twice. The first state change is created
by the signal change, and the second by the timeout of the internal timer. This occurs due to the timer getting
its reset one clock cycle after a state change.
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