U5021M Datasheet, PDF (7/11 Pages) ATMEL Corporation – DIGITAL WINDOW WATCHDOG TIMER

State Diagram
Figure 8. State Diagram
U5021M
The kernel of the watchdog is a finite state machine. Figure 8 shows the state diagram
with all possible states and transmissions. Many transmissions are controlled by an
internal timer. The numbers for the time-outs are the same as on the pulse diagrams.
Reset state
time out t ₀
Mode switch
state
mode = 0
Short window
disable state
mode = 1
mode = 0
Long window
disable state
time out t ₁
time out t ₂
trg_ok = 1
mode = 1
mode = 0
time out t ₄
trg_ok = 1
time out t ₆
trg = 0
time out t ₃
Short window
enable state
Reset out
state
trg_err = 1
trg_err = 1
Long window
enable state
time out t ₅
or
wedge = 1
trg = 0
or wedge = 1
Note:
"mode" and "trg" are the debounced input signals from the pins MODE and TRG
trg_ok = 1 after the rising edge of the trg signal
trg_err = 1 when the trg signal low period is too long
wedge = 1 after detecting the debounced changing of a signal level from the WUP pin
every state change restarts the internal timer
7
4756C–AUTO–09/04