AT91SAM7S64_05 Datasheet, PDF (69/491 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM7S64 Preliminary
15.4.1 Periodic Interval Timer Mode Register
Register Name:
PIT_MR
Access Type:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
PITIEN
PITEN
23
22
21
20
19
18
17
16
–
–
–
–
PIV
15
14
13
12
11
10
9
8
PIV
7
6
5
4
3
2
1
0
PIV
• PIV: Periodic Interval Value
Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to
(PIV + 1).
• PITEN: Period Interval Timer Enabled
0 = The Periodic Interval Timer is disabled when the PIV value is reached.
1 = The Periodic Interval Timer is enabled.
• PITIEN: Periodic Interval Timer Interrupt Enable
0 = The bit PITS in PIT_SR has no effect on interrupt.
1 = The bit PITS in PIT_SR asserts interrupt.
15.4.2 Periodic Interval Timer Status Register
Register Name:
PIT_SR
Access Type:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
PITS
• PITS: Periodic Interval Timer Status
0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.
1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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6070B–ATARM–25-Feb-05