AT91SAM7S64_05 Datasheet, PDF (452/491 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

34.6.7 ADC Last Converted Data Register
Register Name:
ADC_LCDR
Access Type:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
–
–
–
–
–
–
9
8
LDATA
7
6
5
4
3
2
1
0
LDATA
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conver-
sion is completed.
34.6.8 ADC Interrupt Enable Register
Register Name:
ADC_IER
Access Type:
Write-only
31
30
29
–
–
–
23
22
21
–
–
–
15
OVRE7
14
OVRE6
13
OVRE5
7
EOC7
6
EOC6
5
EOC5
28
–
20
–
12
OVRE4
4
EOC4
• EOCx: End of Conversion Interrupt Enable x
• OVREx: Overrun Error Interrupt Enable x
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
27
–
19
RXBUFF
11
OVRE3
3
EOC3
26
–
18
ENDRX
10
OVRE2
2
EOC2
25
–
17
GOVRE
9
OVRE1
1
EOC1
24
–
16
DRDY
8
OVRE0
0
EOC0
452 AT91SAM7S64 Preliminary
6070B–ATARM–25-Feb-05