AT91SAM7X256 Datasheet, PDF (622/637 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

42.2.3
Drive Low NRST, PA0-PA30 and PB0-PB26
When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, driving
the I/O with an output impedance higher than 500 ohms may not drive the I/O to a logical zero.
Problem Fix/Workaround
Output impedance must be lower than 500 ohms.
42.3 Pulse Width Modulation Controller (PWM)
42.3.1
PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Counter Register before writing the update register.
42.3.2
PWM: Update when PWM_CPRDx = 0
When Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround
Do not write 0 in the period register.
42.3.3
PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
Problem Fix/Workaround
None.
42.3.4
PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled
by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of
the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit
in the PWM_SR stays at 1.
Problem Fix/Workaround
Do not disable a channel before completion of one period of the selected clock.
42.4 Serial Peripheral Interface (SPI)
42.4.1
SPI: Bad tx_ready Behavior when CSAAT = 1 and SCBR = 1
If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the tx_ready signal
does not rise after the second data has been transferred in the shifter. This can imply for exam-
ple, that the second data is sent twice.
Problem Fix/Workaround
Do not use the combination CSAAT = 1 and SCBR = 1.
622 AT91SAM7X256/128 Preliminary
6120D–ATARM–02-Feb-06