AT91SAM7X256 Datasheet, PDF (13/637 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM7X256/128 Preliminary
8. Processor and Architecture
8.1 ARM7TDMI Processor
• RISC processor based on ARMv4T Von Neumann architecture
– Runs at up to 55 MHz, providing 0.9 MIPS/MHz
• Two instruction sets
– ARM^® high-performance 32-bit instruction set
– Thumb^® high code density 16-bit instruction set
• Three-stage pipeline architecture
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
8.2 Debug and Test Features
• Integrated EmbeddedICE^™ (embedded in-circuit emulator)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
• Debug Unit
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on all digital pins
8.3 Memory Controller
• Programmable Bus Arbiter
– Handles requests from the ARM7TDMI, the Ethernet MAC and the Peripheral DMA
Controller
• Address decoder provides selection signals for
– Three internal 1 Mbyte memory areas
– One 256 Mbyte embedded peripheral area
• Abort Status Registers
– Source, Type and all parameters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
• Misalignment Detector
– Alignment checking of all data accesses
– Abort generation in case of misalignment
• Remap Command
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
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6120D–ATARM–02-Feb-06