SAM7S512_14 Datasheet, PDF (621/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Problem Fix/Workaround
The data need to be delayed for one bit clock period with an external assembly. In the following schematic, TD, TK
and NRST are SAM7S signals, TXD is the delayed data to connect to the device.
40.6.11 Two-wire Interface (TWI)
40.6.11.1 TWI: Clock Divider
The value of CLDIV x 2^CKDIV must be less than or equal to 8191, the value of CHDIV x 2^CKDIV must be less than or
equal to 8191
Problem Fix/Workaround
None.
40.6.11.2 TWI: Software Reset
When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new trans-
fer in READ or WRITE mode.
Problem Fix/Workaround
None.
40.6.11.3 TWI: Disabling Does not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled
before disabling the TWI.
40.6.11.4 TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit
rising in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission
is not completed.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
621