SAM7S512_14 Datasheet, PDF (16/775 Pages) ATMEL Corporation – ARM-based Flash MCU

7. Processor and Architecture
7.1 ARM7TDMI Processor
z RISC processor based on ARMv4T Von Neumann architecture
z Runs at up to 55 MHz, providing 0.9 MIPS/MHz
z Two instruction sets
z ARM^® high-performance 32-bit instruction set
z Thumb^® high code density 16-bit instruction set
z Three-stage pipeline architecture
z Instruction Fetch (F)
z Instruction Decode (D)
z Execute (E)
7.2 Debug and Test Features
z Integrated EmbeddedICE^™ (embedded in-circuit emulator)
z Two watchpoint units
z Test access port accessible through a JTAG protocol
z Debug communication channel
z Debug Unit
z Two-pin UART
z Debug communication channel interrupt handling
z Chip ID Register
z IEEE1149.1 JTAG Boundary-scan on all digital pins
7.3 Memory Controller
z Bus Arbiter
z Handles requests from the ARM7TDMI and the Peripheral DMA Controller
z Address decoder provides selection signals for
z Three internal 1 Mbyte memory areas
z One 256 Mbyte embedded peripheral area
z Abort Status Registers
z Source, Type and all parameters of the access leading to an abort are saved
z Facilitates debug by detection of bad pointers
z Misalignment Detector
z Alignment checking of all data accesses
z Abort generation in case of misalignment
z Remap Command
z Remaps the SRAM in place of the embedded non-volatile memory
z Allows handling of dynamic exception vectors
z Embedded Flash Controller
z Embedded Flash interface, up to three programmable wait states
z Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states
z Key-protected program, erase and lock/unlock sequencer
z Single command for erasing, programming and locking operations
z Interrupt generation in case of forbidden operation
SAM7S Series [DATASHEET] 16
6175M–ATARM–26-Oct-12