AT17F16_14 Datasheet, PDF (6/20 Pages) ATMEL Corporation – In-System Programmable (ISP) via 2-wire Bus

5.10 READY
5.11 SER_EN⁽¹⁾
5.12 V_CC
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7 kΩ pull-up on this pin if used).
The serial enable input must remain High during FPGA configuration operations. Bringing
SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V_CC.
+3.3V (±10%).
Notes: 1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
6 AT17F16
3392F–CNFG–2/08