AT17F16_14 Datasheet, PDF (4/20 Pages) ATMEL Corporation – In-System Programmable (ISP) via 2-wire Bus

5. Pin Description
5.1 DATA⁽¹⁾
Table 5-1. Pin Description
Name
I/O
DATA
I/O
CLK
I
PAGE_EN
I
PAGESEL0
I
PAGESEL1
I
RESET/OE
I
CE
I
GND
–
CEO
O
A2
I
READY
O
SER_EN
I
V_CC
–
8
LAP
1
2
–
–
–
3
4
5
6
–
7
8
AT17F16
20
PLCC
2
4
16
11
7
6
8
10
14
15
17
20
44
TQFP
40
43
39
14
19
13
15
18
21
23
35
38
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2 CLK⁽¹⁾
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5.3 PAGE_EN⁽²⁾
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes: 1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
4 AT17F16
3392F–CNFG–2/08