AT91SAM7XC512_1 Datasheet, PDF (589/727 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM7XC512/256/128 Preliminary
38.8.6 CAN Baudrate Register
Name:
CAN_BR
Access Type:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
SMP
23
22
21
20
19
18
17
16
–
BRP
15
14
13
12
11
10
9
8
–
–
SJW
–
PROPAG
7
6
5
4
3
2
1
0
–
PHASE1
–
PHASE2
Any modification on one of the fields of the CANBR register must be done while CAN module is disabled.
To compute the different Bit Timings, please refer to the Section 38.6.4.1 “CAN Bit Timing Configuration” on page 556.
• PHASE2: Phase 2 segment
This phase is used to compensate the edge phase error.
t_PHS2 = t_CSC × (PHASE2 + 1)
Warning: PHASE2 value must be different from 0.
• PHASE1: Phase 1 segment
This phase is used to compensate for edge phase error.
t_PHS1 = t_CSC × (PHASE1 + 1)
• PROPAG: Programming time segment
This part of the bit time is used to compensate for the physical delay times within the network.
t_PRS = t_CSC × (PROPAG + 1)
• SJW: Re-synchronization jump width
To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize
on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock
cycles a bit period may be shortened or lengthened by re-synchronization.
t_SJW = t_CSC × (SJW + 1)
• BRP: Baudrate Prescaler.
This field allows user to program the period of the CAN system clock to determine the individual bit timing.
t_CSC = (BRP + 1) ⁄ MCK
The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.
• SMP: Sampling Mode
0 = The incoming bit stream is sampled once at sample point.
1 = The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.
SMP Sampling Mode is automatically disabled if BRP = 0.
6209F–ATARM–17-Feb-09
589