AT91SAM7XC512_1 Datasheet, PDF (267/727 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM7XC512/256/128 Preliminary
Figure 28-8 shows different peripheral deselection cases and the effect of the CSAAT bit.
Figure 28-8. Peripheral Deselection
CSAAT = 0
CSAAT = 1
TDRE
NPCS[0..3]
Write SPI_TDR
DLYBCT
A
A
DLYBCS
PCS = A
DLYBCT
A
A
A
DLYBCS
PCS = A
TDRE
NPCS[0..3]
Write SPI_TDR
DLYBCT
A
A
DLYBCS
PCS=A
DLYBCT
A
A
A
DLYBCS
PCS = A
TDRE
DLYBCT
NPCS[0..3]
A
Write SPI_TDR
B
DLYBCS
PCS = B
DLYBCT
A
B
DLYBCS
PCS = B
28.6.3.8
Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be con-
figured in open drain through the PIO controller, so that external pull up resistors are needed to
guarantee high level.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and
the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Con-
trol Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault
detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
28.6.4
SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
6209F–ATARM–17-Feb-09
267