AT90PWM1_14 Datasheet, PDF (56/297 Pages) ATMEL Corporation – Advanced RISC Architecture

0xC01
0xC02
0xC03
0xC04
0xC05
out SPH,r16
; Set Stack Pointer to top of RAM
ldi r16,low(RAMEND)
out SPL,r16
sei
; Enable interrupts
<instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in AT90PWM1 is:
Address Labels Code
Comments
;
.org 0xC00
0xC00
rjmp RESET
; Reset handler
0xC01
rjmp PSC2_CAPT
; PSC2 Capture event Handler
0xC02
rjmp PSC2_EC
; PSC2 End Cycle Handler
...
... ...
;
0xC1F
rjmp SPM_RDY
; Store Program Memory Ready Handler
;
0xC20 RESET: ldi r16,high(RAMEND); Main program start
0xC21
out SPH,r16
; Set Stack Pointer to top of RAM
0xC22
ldi r16,low(RAMEND)
0xC23
0xC24
out SPL,r16
sei
; Enable interrupts
0xC25
<instr> xxx
10.1.1
10.1.2
Moving Interrupts Between Application and Boot Space
The MCU Control Register controls the placement of the Interrupt Vector table.
MCU Control Register – MCUCR
Bit
7
6
SPIPS
–
Read/Write
R/W
R
Initial Value
0
0
5
4
3
–
PUD
–
R
R/W
R
0
0
0
2
1
0
–
IVSEL
IVCE
MCUCR
R
R/W
R/W
0
0
0
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write
Self-Programming” on page 205 for details. To avoid unintentional changes of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
56 AT90PWM1
4378C–AVR–09/08