AT90PWM1_14 Datasheet, PDF (17/297 Pages) ATMEL Corporation – Advanced RISC Architecture

AT90PWM1
6. Memories
This section describes the different memories in the AT90PWM1. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
AT90PWM1 features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
6.1 In-System Reprogrammable Flash Program Memory
The AT90PWM1 contains 8K bytes On-chip In-System Reprogrammable Flash memory for pro-
gram storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x
16. For software security, the Flash Program memory space is divided into two sections, Boot
Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90PWM1
Program Counter (PC) is 12 bits wide, thus addressing the 4K program memory locations. The
operation of Boot Program section and associated Boot Lock bits for software protection are
described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page
205. “Memory Programming” on page 219 contains a detailed description on Flash programming
in SPI or Parallel programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory.
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 13.
Figure 1. Program Memory Map
Program Memory
0x0000
Application Flash Section
Boot Flash Section
0x0FFF
6.2 SRAM Data Memory
Figure 2 shows how the AT90PWM1 SRAM Memory is organized.
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