PC7457 Datasheet, PDF (54/66 Pages) ATMEL Corporation – PowerPC 7457 RISC Microprocessor

PLL Power Supply
Filtering
Decoupling
Recommendations
The AV_DD power signal is provided on the PC7457 to provide power to the clock gener-
ation PLL. To ensure stability of the internal clock, the power supplied to the AV_DD input
signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency
range of the PLL. A circuit similar to the one shown in Figure 29 using surface mount
capacitors with minimum effective series inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AV_DD pin to minimize noise cou-
pled from nearby circuits. It is often possible to route directly from the capacitors to the
AV_DD pin, which is on the periphery of the 360 CBGA footprint and very close to the
periphery of the 483 CBGA footprint, without the inductance of vias.
The PLL power supply filter provided in the PC7457 RISC Microprocessor Hardware
Specifications has been found to be less effective for Rev 1.1 devices with the low core
voltages described in this specification.
As a result, the recommended value for the resistor in the circuit is being evaluated and
a new recommendation is indicated in Figure 31. Motorola continues to evaluate the fil-
tering requirements of the PC7457 and will make updated recommendations as needed.
Note that this recommendation applies to Rev. 1.1 devices only.
Figure 31. PLL Power Supply Filter Circuit
400Ω
VDD
2.2 µF
2.2 µF
AVDD
Low ESL surface mount capacitor
GND
Due to the PC7457 dynamic power management feature, large address and data buses,
and high operating frequencies, the PC7457 can generate transient power surges and
high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the PC7457 system,
and the PC7457 itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each
V_DD, OV_DD, and GV_DD pin of the PC7457. It is also recommended that these decoupling
capacitors receive their power from separate V_DD, OV_DD/GV_DD, and GND power planes
in the PCB, utilizing short traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount
technology (SMT) capacitors should be used to minimize lead inductance, preferably
0508 or 0603 orientations where connections are made along the length of the part.
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital
Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous rec-
ommendations for decoupling Motorola microprocessors, multiple small capacitors of
equal value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed
around the PCB, feeding the V_DD, GV_DD, and OV_DD planes, to enable quick recharging
of the smaller chip capacitors. These bulk capacitors should have a low equivalent
series resistance (ESR) rating to ensure the quick response time necessary. They
should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors: 100 – 330 µF (AVX TPS tantalum or Sanyo
OSCON).
54 PC7457/47 [Preliminary]
5345B–HIREL–02/04