PC7457 Datasheet, PDF (30/66 Pages) ATMEL Corporation – PowerPC 7457 RISC Microprocessor

Figure 13 shows the typical connection diagram for the PC7457 interfaced to MSUG2 DDR SRAMs.
Figure 13. Typical Source Synchronous 4M bytes L3 Cache DDR Interface
PC7457
Denotes
Receive (SRAM
to PC7457)
Aligned Signals
Denotes
Transmit
(PC7457 to SRAM)
Aligned Signals
L3ADDR[18:0]
L3_CNTL[0]
L3_CNTL[1]
L3_ECHO_CLK[0]
{L3DATA[0:15], L3DP[0:1]}
L3_CLK[0]
{L3DATA[16:31], L3DP[2:3]}
L3_ECHO_CLK[1]
L3ECHO_CLK[2]
{L3DATA[32:47], L3DP[4:5]}
L3_CLK[1]
{L3DATA[48:63], L3DP[6:7]}
L3_ECHO_CLK[3]
SRAM 0
SA[18:0]
B3
B1
G
B2
CQ
D[0:17]
LBO
CQ
CK
CQ
D[18:35]
CK
CQ
GND
GND
GND
NC
NC
GVDD/2 ⁽¹⁾
SRAM 1
SA[18:0]
B3
B1
B2
G
CQ
LBO
D[0:17]
CQ
CK
CQ
D[18:35]
CK
CQ
GND
GND
GND
NC
NC
GVDD/2 ⁽¹⁾
Note: 1. Or as recommended by SRAM manufacturer for single-ended clocking.
30 PC7457/47 [Preliminary]
5345B–HIREL–02/04