ATTINY841_14 Datasheet, PDF (53/366 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 4/8K Bytes In-System

 Bit 6 – INT0: External Interrupt Request 0 Enable
The external interrupt for pin INT0 is enabled when this bit and the I-bit in the Status Register (SREG) are set. The trigger
conditions are set with the ISC0n bits.
Activity on the pin will cause an interrupt request even if INT0 has been configured as an output.
 Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When this bit and the I-bit of SREG are set the Pin Change Interrupt 1 is enabled. Any change on an enabled
PCINT[11:8] pin will cause a PCINT1 interrupt. See Table 9-1 on page 49.
Each pin can be individually enabled. See “PCMSK1 – Pin Change Mask Register 1” on page 54.
 Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When this bit and the I-bit of SREG are set the Pin Change Interrupt 0 is enabled. Any change on an enabled PCINT[7:0]
pin will cause a PCINT0 interrupt. See Table 9-1 on page 49.
Each pin can be individually enabled. See “PCMSK0 – Pin Change Mask Register 0” on page 54.
 Bits 3:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
9.3.3 GIFR – General Interrupt Flag Register
Bit
0x3A (0x5A)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
–
INTF0
PCIF1
PCIF0
–
–
–
–
GIFR
R
R/W
R/W
R/W
R
R
R
R
0
0
0
0
0
0
0
0
 Bit 7 – Res: Reserved Bit
This bit is reserved and will always read zero.
 Bit 6 – INTF0: External Interrupt Flag 0
This bit is set when activity on INT0 has triggered an interrupt request. Provided that the I-bit in SREG and the INT0 bit
are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
 Bit 1 – PCIF1: Pin Change Interrupt Flag 1
This bit is set when a logic change on any PCINT[11:8] pin has triggered an interrupt request. Provided that the I-bit in
SREG and the PCIE1 bit in PCICR are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
 Bit 0 – PCIF0: Pin Change Interrupt Flag 0
This bit is set when a logic change on any PCINT[7:0] pin has triggered an interrupt request. Provided that the I-bit in
SREG and the PCIE0 bit in PCICR are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
ATtiny441/841 [DATASHEET] 53
8495H–AVR–05/2014