ATTINY841_14 Datasheet, PDF (100/366 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 4/8K Bytes In-System

are affected by the COMnx[1:0] bits are shown. When referring to the OCnx state, the reference is for the internal OCnx
Register, not the OCnx pin. If a system reset occur, the OCnx Register is reset to “0”.
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the
COMnx[1:0] bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction
Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output
before the OCnx value is visible on the pin. The port override function is generally independent of the Waveform
Generation mode, but there are some exceptions. See Table 12-2 on page 112, Table 12-3 on page 112 and Table 12-4
on page 112 for details.
The design of the Output Compare pin logic allows initialization of the OCnx state before the output is enabled. Note that
some COMnx[1:0] bit settings are reserved for certain modes of operation. See “Register Description” on page 111
The COMnx[1:0] bits have no effect on the Input Capture unit.
12.8.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COMnx[1:0] bits differently in normal, CTC, and PWM modes. For all modes, setting
the COMnx[1:0] = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next
compare match. For compare output actions in the non-PWM modes refer to Table 12-2 on page 112. For fast PWM
mode refer to Table 12-3 on page 112, and for phase correct and phase and frequency correct PWM refer to Table 12-4
on page 112.
A change of the COMnx[1:0] bits state will have effect at the first compare match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the FOCnx strobe bits.
12.9
Modes of Operation
The mode of operation, i.e., the behavior of the timer/counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGMn[3:0]) and Compare Output mode (COMnx[1:0]) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The
COMnx[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
For non-PWM modes the COMnx[1:0] bits control whether the output should be set, cleared or toggle at a compare
match (“Compare Match Output Unit” on page 99)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 106.
12.9.1 Normal Mode
The simplest mode of operation is the Normal mode (WGMn[3:0] = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value
(MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag
(TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn flag in this case behaves like a
17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically
clears the TOVn flag, the timer resolution can be increased by software. There are no special cases to consider in the
Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external
events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow
interrupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
12.9.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGMn[3:0] = 4 or 12), the OCRnA or ICRn Register are used to manipulate
the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches either the
OCRnA (WGMn[3:0] = 4) or the ICRn (WGMn[3:0] = 12). The OCRnA or ICRn define the top value for the counter, hence
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