AT17F16A_14 Datasheet, PDF (5/16 Pages) ATMEL Corporation – Simple Interface to SRAM FPGAs

AT17F16A
5.4 PAGESEL[1:0]⁽²⁾
Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 5-2. When
SER_EN is Low (ISP mode) these pins have no effect.
Table 5-2. Address Space
Paging Decodes
PAGESEL = 00, PAGE_EN = 1
PAGESEL = 01, PAGE_EN = 1
PAGESEL = 10, PAGE_EN = 1
PAGESEL = 11, PAGE_EN = 1
PAGESEL = XX, PAGE_EN = 0
AT17F16A (16 Mbits)
00000 – 3FFFFh
40000 – 7FFFFh
80000 – BFFFFh
C0000 – FFFFFh
00000 – FFFFFh
5.5 RESET/OE⁽¹⁾
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the
data output driver.
5.6 nCS⁽¹⁾
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the
address counter and enables the data output driver. A High level on nCS disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7 GND
5.8 nCASC
Ground pin. A 0.2 µF decoupling capacitor between V_CC and GND is recommended.
Cascade Select Output (when SER_EN is High). This output goes Low when the internal
address counter has reached its maximum value. If the PAGE_EN input is set High, the maxi-
mum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used
to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned
and the address maximum value is the highest address in the device, see Table 5-2 on page 5.
In a daisy chain of AT17FxxA Series devices, the nCASC pin of one device must be connected
to the nCS input of the next device in the chain. It will stay Low as long as nCS is Low and OE is
High. It will then follow nCS until OE goes Low; thereafter, nCASC will stay High until the entire
EEPROM is read again.
Notes: 1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
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