AT17F16A_14 Datasheet, PDF (10/16 Pages) ATMEL Corporation – Simple Interface to SRAM FPGAs

16. AC Characteristics
Symbol
T_OE(2)
T_CE(2)
T_CAC(2)
T_OH
T_DF(3)
T_LC
T_HC
T_SCE
T_HCE
T_HOE
F_MAX
T_WR
T_EC
Description
OE to Data Delay
nCS to Data Delay
DCLK to Data Delay
Data Hold from nCS, OE, or DCLK
nCS or OE to Data Float Delay
DCLK Low Time
DCLK High Time
nCS Setup Time to DCLK
(to guarantee proper counting)
nCS Hold Time from DCLK
(to guarantee proper counting)
RESET/OE Low Time
(guarantees counter is reset)
Maximum Input Clock Frequency
SEREN = 0 (in 2-wire mode)
Write Cycle Time⁽⁴⁾
Erase Cycle Time⁽⁴⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
Commercial
Industrial⁽¹⁾
AT17F16A
Min
Typ
Max
Units
50
ns
55
ns
55
ns
60
ns
30
ns
30
ns
0
ns
0
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
20
ns
25
ns
0
ns
0
ns
20
ns
20
ns
10
MHz
10
MHz
12
µs
12
µs
25
s
25
s
Notes:
1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady-state active levels.
4. See the AT17FxxA Programming Specification for procedural information.
5. Times given are per byte typical.
10 AT17F16A
3474E–CNFG–2/08