AT32UC3L064_2 Datasheet, PDF (477/830 Pages) ATMEL Corporation – 32-bit AVR® Microcontroller

AT32UC3L016/32/64
22.8.2.1
Clock Generation
The Clock Waveform Generator Register (CWGR) is used to control the waveform of the
TWCK clock. CWGR must be programmed so that the desired TWI bus timings are generated.
CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescal-
ing can be selected through the EXP field in CWGR.
f_prescaled = _2----(--_E-^f--^cX--^l-_P-^k--^p-₊--^b--₁---₎--₎
CWGR has the following fields:
LOW: Prescaled clock cycles in clock low count. Used to time T_LOW. and T_BUF.
HIGH: Prescaled clock cycles in clock high count. Used to time T_HIGH.
STASTO: Prescaled clock cycles in clock high count. Used to time T_{HD_STA}, T_{SU_STA}, T_{SU_STO}.
DATA: Prescaled clock cycles for data setup and hold count. Used to time T_{HD_DAT}, T_{SU_DAT}.
EXP: Specifies the clock prescaler setting.
Note that the total clock low time generated is the sum of T_{HD_DAT} + T_{SU_DAT} + T_LOW.
Any slave or other bus master taking part in the transfer may extend the TWCK low period at
any time.
The TWIM hardware monitors the state of the TWCK line as required by the I²C specification.
The clock generation counters are started when a high/low level is detected on the TWCK line,
not when the TWIM hardware releases/drives the TWCK line. This means that the CWGR set-
tings alone do not determine the TWCK frequency. The CWGR settings determine the clock
low time and the clock high time, but the TWCK rise and fall times are determined by the exter-
nal circuitry (capacitive load, etc.).
Figure 22-5. Bus Timing Diagram
t _LOW
t _HIGH
t _LOW
S
t _HD:STA
t
SU:DAT
t _HD:DAT
t _SU:DAT
t
SU:STO
P
t _SU:STA
Sr
22.8.2.2
Setting up and Performing a Transfer
Operation of TWIM is mainly controlled by the Control Register (CR) and the Command Reg-
ister (CMDR). The following list presents the main steps in a typical communication:
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