AT32UC3L064_2 Datasheet, PDF (340/830 Pages) ATMEL Corporation – 32-bit AVR® Microcontroller

AT32UC3L016/32/64
ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g.
IFR), not all access methods are permitted.
Note that for ports with less than 32 bits, the corresponding control registers will have unused
bits. This is also the case for features that are not implemented for a specific pin. Writing to an
unused bit will have no effect. Reading unused bits will always return 0.
19.7.2
Configuration Protection
In order to protect the configuration of individual GPIO pins from software failure, configuration
bits for individual GPIO pins may be locked by writing a one to the corresponding bit in the LOCK
register. While this bit is one, any write to the same bit position in any lockable GPIO register
using the Peripheral Bus (PB) will not have an effect. The CPU Local Bus is not checked and
thus allowed to write to all bits in a CPU Local Bus mapped register no mather the LOCK value.
The registers required to clear bits in the LOCK register are protected by the access protection
mechanism described in Section 19.7.3, ensuring the LOCK mechanism itself is robust against
software failure.
19.7.3
Access Protection
In order to protect critical registers from software failure, some registers are protected by a key
protection mechanism. These registers can only be changed by first writing the UNLOCK regis-
ter, then the protected register. Protected registers are indicated in Table 19-2. The UNLOCK
register contains a key field which must always be written to 0xAA, and an OFFSET field corre-
sponding to the offset of the register to be modified.
The next write operation resets the UNLOCK register, so if the register is to be modified again,
the UNLOCK register must be written again.
Attempting to write to a protected register without first writing the UNLOCK register results in the
write operation being discarded, and the Access Error bit in the Access Status Register
(ASR.AE) will be set.
Table 19-2.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
GPIO Register Memory Map
Register
GPIO Enable Register
GPIO Enable Register
GPIO Enable Register
GPIO Enable Register
Peripheral Mux Register 0
Peripheral Mux Register 0
Peripheral Mux Register 0
Peripheral Mux Register 0
Peripheral Mux Register 1
Peripheral Mux Register 1
Peripheral Mux Register 1
Function
Read/Write
Set
Clear
Toggle
Read/Write
Set
Clear
Toggle
Read/Write
Set
Clear
Register Name
GPER
GPERS
GPERC
GPERT
PMR0
PMR0S
PMR0C
PMR0T
PMR1
PMR1S
PMR1C
Access
Read/Write
Write-only
Write-only
Write-only
Read/Write
Write-only
Write-only
Write-only
Read/Write
Write-only
Write-only
Reset
-⁽¹⁾
-⁽¹⁾
-⁽¹⁾
Config.
Protection
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Access
Protection
N
N
N
N
N
N
N
N
N
N
N
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