AT91SAM9263_1 Datasheet, PDF (474/1110 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

AT91SAM9263 Preliminary
32.7.9 SPI Chip Select Register
Name:
SPI_CSR0... SPI_CSR3
Addresses: 0xFFFA4030 (0), 0xFFFA8030 (1)
Access Type: Read/Write
31
30
29
28
27
26
25
24
DLYBCT
23
22
21
20
19
18
17
16
DLYBS
15
14
13
12
11
10
9
8
SCBR
7
6
5
4
3
2
1
0
BITS
CSAAT
–
NCPHA
CPOL
Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans-
lated value unless the register is written.
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
• BITS: Bits Per Transfer (See the ^(Note:) below the register table; Section 32.7.9 “SPI Chip Select Register” on page 474.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS
0000
0001
0010
0011
0100
0101
0110
0111
Bits Per Transfer
8
9
10
11
12
13
14
15
6249H–ATARM–27-Jul-09
474