AT91SAM9263_1 Datasheet, PDF (461/1110 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

AT91SAM9263 Preliminary
Figure 32-8. Peripheral Deselection
CSAAT = 0 and CSNAAT = 0
TDRE
NPCS[0..3]
Write SPI_TDR
DLYBCT
A
A
DLYBCS
PCS = A
CSAAT = 1 and CSNAAT= 0 / 1
DLYBCT
A
A
A
DLYBCS
PCS = A
TDRE
NPCS[0..3]
Write SPI_TDR
DLYBCT
A
A
DLYBCS
PCS=A
DLYBCT
A
A
A
DLYBCS
PCS = A
TDRE
DLYBCT
NPCS[0..3]
A
B
DLYBCS
PCS = B
Write SPI_TDR
DLYBCT
A
B
DLYBCS
PCS = B
32.6.3.8
Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be con-
figured in open drain through the PIO controller, so that external pull up resistors are needed to
guarantee high level.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and
the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Con-
trol Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault
detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
32.6.4
SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed
following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the
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