AT91SAM9263_1 Datasheet, PDF (241/1110 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

AT91SAM9263 Preliminary
23.5.4
SDRAM Controller Refresh Cycles
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is
loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles
between refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform.
It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the
device is busy and the master is held by a wait signal. See Figure 23-5.
Figure 23-5. Refresh Cycle Followed by a Read Access
SDCS
t_RP = 3
t_RC = 8
t_RCD = 3
CAS = 2
SDCK
Row n
SDRAMC_A[12:0] col c col d
RAS
CAS
Row m
col a
SDWE
D[31:0]
(input)
Dnb Dnc Dnd
Dma
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