ATMEGA128RFR2_14 Datasheet, PDF (462/611 Pages) ATMEL Corporation – Microcontroller with Low Power

connected to a differential input channel with a gain of 10. The voltage offset error of
the differential signal processing can be corrected to the first order by using an
appropriate similar channel (e.g. MUX4:0=01000, MUX5=0, see Table 27-12 on page
465). The ADC result of this channel is then subtracted from the ADC result of the
temperature sensor. Offset errors are typically only +1 bit (ADC = 0x001) or -1 bit (ADC
= 0x3ff).
Note:
1. For the ATmega128RFA1 changing between the temperature sensor channel and
the channel for the offset error correction requires to disable the ADC, select the
new channel and then enable the ADC again, or to discard the first conversion
result from the new input channel.
27.10 SRAM DRT Voltage Measurement
The decrease of the supply voltage of SRAM block 2 for the leakage current reduction
can also be measured using a special setup of the A/D converter inputs. The details of
the SRAM leakage current reduction are described in section "SRAM with Data
Retention" on page 193. The supply voltage of a disabled SRAM block can be reduced
to save leakage power while maintaining data retention. This feature applies to all four
SRAM blocks however only the voltage of SRAM block 2 can be verified using the A/D
converter.
The default factory setting for the data retention (DRT) voltage normally guarantees the
best leakage performances. Other values are nevertheless possible and can be
selected by the application software. The true value of the supply voltage reduction is
depending on the manufacturing process and environmental conditions like
temperature. The A/D converter allows determining the value of the DRT voltage of
SRAM block 2. The same voltage setting results for all practical purposes in the same
supply voltage for all other SRAM blocks.
Care must be taken when verifying the DRT voltage of SRAM block 2 with the A/D
converter because it will be put into sleep mode and hence it is not available for the
application program. Addressing the disabled SRAM will return invalid data (all data
read zero). The voltage measurement is split into two parts. One setting allows
measuring the voltage drop from DVDD. The other setting allows verifying the voltage
shift from DVSS. Both measurements are differential and use the programmable gain
amplifier. A low frequency of the conversion clock must be selected due to the high-
impedance nature of the input signal. Accurate and stable voltage readings may just be
available after a long waiting time of up to 100 ms. This limitation is the consequence of
the small leakage currents that discharge the internal de-coupling capacitances before
the supply voltage settles to the DRT value. The following table summarizes the
preferred setup of the DRT voltage measurement:
Table 27-9. Recommended ADC Setup for DRT Voltage Measurements
Parameter
Register Recommended Setup
SRAM DRT on DRTRAM2 Set bits DISPC and ENDRT to 1;
ADC Channel ADMUX,
ADCSRB
Select MUX4:0 = 10100 to measure VDRTBBP;
Select MUX4:0 = 11101 to measure VDRTBBN;
MUX5 = 1;
ADC Clock
ADCSRA Select a clock frequency of 500kHz or lower;
VREF
ADMUX
Select the internal 1.6V reference voltage;
Start-up time ADCSRC Standard requirement of 20µs is sufficient;
Tracking time ADCSRC Setting ADTHT = 0 is sufficient;
462 _{ATmega256/128/64RFR2}
8393C-MCU Wireless-09/14