ATMEGA128RFR2_14 Datasheet, PDF (213/611 Pages) ATMEL Corporation – Microcontroller with Low Power

ATmega256/128/64RFR2
13.4 Watchdog Timer
13.4.1 Features
• Clocked from separate On-chip Oscillator
• 3 Operating modes
- Interrupt
- System Reset
- Interrupt and System Reset
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
Figure 13-7. Watchdog Timer
128kHz
OSCILLATOR
13.4.2 Overview
WATCHDOG
RESET
WDE
WDIF
WDIE
WDP0
WDP1
WDP2
WDP3
MCU RESET
INTERRUPT
ATmega256/128/64RFR2 has an Enhanced Watchdog Timer (WDT). The WDT is a
timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an
interrupt or a system reset when the counter reaches a given time-out value. In normal
operation mode, it is required that the system uses the WDR -Watchdog Timer Reset -
instruction to restart the counter before the time-out value is reached. If the system
doesn't restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can
be used to wake the device from sleep-modes, and also as a general system timer.
One example is to limit the maximum time allowed for certain operations, giving an
interrupt when the operation has run longer than expected. In System Reset mode, the
WDT gives a reset when the timer expires. This is typically used to prevent system
hang-up in case of runaway code. The third mode, Interrupt and System Reset mode,
combines the other two modes by first giving an interrupt and then switch to System
Reset mode. This mode will for instance allow a safe shutdown by saving critical
parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer
to System Reset mode. With the fuse programmed the System Reset mode bit (WDE)
and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure
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