ATMEGA256RFR2_14 Datasheet, PDF (446/611 Pages) ATMEL Corporation – Microcontroller with Low Power

27.3 ADC Start-Up
changes in the course of the successive approximation process (load current steps).
The internal voltage reference (except AVDD) must not be decoupled by an external
capacitor. Adding unnecessary external capacitance at the AREF pin will cause instable
operation of the internal reference voltage buffer and will not improve noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX and
ADCSRB. Any of the ADC input pins, as well as AVSS and a fixed bandgap voltage
reference can be selected as single ended inputs to the ADC. A choice of ADC input
pins can be selected as positive and negative inputs to the differential amplifier.
Furthermore the temperature sensor and the DRT voltages of SRAM2 can also be
processed with the ADC.
If differential channels are selected, the amplified voltage difference between the
selected input channel pair then becomes the input of the ADC. The respective pin
voltages for a differential measurement can be in the range from 0V to EVDD. In this
way it is possible to handle differential input voltages with a common mode value higher
than AVDD e.g. process a 50mV differential signal with a 2.5V common mode voltage.
If single ended channels are used, the gain amplifier is bypassed altogether. Any ADC
input voltage (single-ended or amplified-differential) exceeding AVDD will be internally
clamped to AVDD to avoid damaging the ADC circuitry. Note that the pin input current
will not increase if the clamp circuit is active.
The ADC is enabled by setting ADEN bit in ADCSRA. Voltage reference and input
channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared. It is required to disable the ADC before entering power
saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionally
be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the
content of the Data Registers belongs to the same conversion. Once ADCL is read,
ADC access to Data Registers is blocked. This means that if ADCL has been read, and
a conversion completes before ADCH is read, neither register is updated and the result
from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL
Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes.
When ADC access to the Data Registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.
After the ADC is enabled by setting ADEN, it will go through a start-up phase. The
analog supply voltage AVDD is turned on. It takes time t_AVREG (see "Power Management
Electrical Characteristics" on page 557) µs for AVDD to stabilize. A stable AVDD
voltage is indicated by the AVDDOK bit in ADCSRB. After this the ADC and, for
differential input channels also the gain amplifier, is powered up. The duration of this
phase depends on the ADC clock period and the configuration of the Start-Up and
Track-And–Hold Time bits, ADSUT and ADTHT in ADCSRC. For details about the start-
up timing refer to section "Pre-scaling and Conversion Timing" on page 448.
During the ADC start-up phase a conversion start can already be requested by writing a
logical one to the ADC Start Conversion bit, ADSC in ADCSRA. In this case a
conversion is started directly after the start-up phase. During the start-up phase it is still
446 _{ATmega256/128/64RFR2}
8393C-MCU Wireless-09/14