ATMEGA256RFR2_14 Datasheet, PDF (370/611 Pages) ATMEL Corporation – Microcontroller with Low Power

These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency fosc is shown in the following table.
Table 22-5 SPR Register Bits
Register Bits
Value
Description
SPR1:0
0x00
0x01
0x02
0x03
fosc/4 / fosc/2 (SPI2X=0/1)
fosc/16 / fosc/8 (SPI2X=0/1)
fosc/64 / fosc/32 (SPI2X=0/1)
fosc/128 / fosc/64 (SPI2X=0/1)
22.4.2 SPSR – SPI Status Register
Bit
7
6
5
$2D ($4D)
Read/Write
Initial Value
SPIF
R
0
WCOL
R
0
Res4
R
0
4
Res3
R
0
3
Res2
R
0
2
Res1
R
0
1
Res0
R
0
0
SPI2X
RW
0
SPSR
• Bit 7 – SPIF - SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if
SPIE in SPCR is set and global interrupts are enabled. The SPIF Flag is also set if the
Slave Select pin is an input and is driven low when the SPI is in Master mode. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF
set and then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL - Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register
with WCOL set and then accessing the SPI Data Register.
• Bit 5:1 – Res4:0 - Reserved
• Bit 0 – SPI2X - Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in Master mode. This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work
at fosc/4 or lower. The SPI interface is also used for program memory and EEPROM
downloading or uploading. See section "Serial Downloading" for serial programming
and verification.
22.4.3 SPDR – SPI Data Register
Bit
7
6
5
4
3
2
1
0
$2E ($4E)
SPDR7:0
Read/Write RW RW RW RW RW RW
R
R
Initial Value X
X
X
X
X
X
0
0
SPDR
370 _{ATmega256/128/64RFR2}
8393C-MCU Wireless-09/14