AT25DF641 Datasheet, PDF (41/59 Pages) ATMEL Corporation – 64-Megabit 2.7-volt Minimum SPI Serial Flash Memory

AT25DF641 [Preliminary]
11.3
Write Status Register Byte 2
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Sta-
tus Register. Using the Write Status Register Byte 2 command is the only way to modify the
RSTE and SLE bits in the Status Register during normal device operation, and the SLE bit can
only be modified if the sector lockdown state has not been frozen. Before the Write Status Reg-
ister Byte 2 command can be issued, the Write Enable command must have been previously
issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the
opcode of 31h must be clocked into the device followed by one byte of data. The one byte of
data consists of three don’t care bits, the RSTE bit value, the SLE bit value, and three additional
don’t care bits (see Table 11-4). Any additional data bytes that are sent to the device will be
ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status Register will be
modified, and the WEL bit in the Status Register will be reset back to a logical “0”. The SLE bit
will only be modified if the Freeze Sector Lockdown State command has not been previously
issued.
The complete one byte of data must be clocked into the device before the CS pin is deasserted,
and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise,
the device will abort the operation, the state of the RSTE and SLE bits will not change, and the
WEL bit in the Status Register will be reset back to the logical “0” state.
Table 11-4.
Bit 7
X
Write Status Register Byte 2 Format
Bit 6
Bit 5
Bit 4
Bit 3
X
X
RSTE
SLE
Bit 2
X
Bit 1
X
Bit 0
X
Figure 11-3. Write Status Register Byte 2
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OPCODE
STATUS REGISTER IN
BYTE 2
0 0 1 1 0 0 0 1 XXXDDXXX
MSB
MSB
HIGH-IMPEDANCE
41
3680E–DFLASH–12/08