AT25DF641 Datasheet, PDF (40/59 Pages) ATMEL Corporation – 64-Megabit 2.7-volt Minimum SPI Serial Flash Memory

11.2
Write Status Register Byte 1
The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Regis-
ter and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status
Register Byte 1 command can be issued, the Write Enable command must have been previ-
ously issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register Byte 1 command, the CS pin must first be asserted and the
opcode of 01h must be clocked into the device followed by one byte of data. The one byte of
data consists of the SPRL bit value, a don’t care bit, four data bits to denote whether a Global
Protect or Unprotect should be performed, and two additional don’t care bits (see Table 11-3).
Any additional data bytes that are sent to the device will be ignored. When the CS pin is deas-
serted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status
Register will be reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the
SPRL bit before the Write Status Register Byte 1 command was executed (the prior state of the
SPRL bit) will determine whether or not a Global Protect or Global Unprotect will be performed.
Please refer to “Global Protect/Unprotect” on page 24 for more details.
The complete one byte of data must be clocked into the device before the CS pin is deasserted,
and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise,
the device will abort the operation, the state of the SPRL bit will not change, no potential Global
Protect or Unprotect will be performed, and the WEL bit in the Status Register will be reset back
to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made
to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register
Byte 1 command will be ignored, and the WEL bit in the Status Register will be reset back to the
logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
Table 11-3.
Bit 7
SPRL
Write Status Register Byte 1 Format
Bit 6
Bit 5
Bit 4
Bit 3
X
Global Protect/Unprotect
Bit 2
Bit 1
X
Bit 0
X
Figure 11-2. Write Status Register Byte 1
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OPCODE
STATUS REGISTER IN
BYTE 1
0 0 0 0 0 0 0 1DXDDDDXX
MSB
MSB
HIGH-IMPEDANCE
40 AT25DF641 [Preliminary]
3680E–DFLASH–12/08